The use of a quartz mask board with the use of chromium for exposing a semiconductor substrate has been determined to cause optical interference between neighboring patterns with reduced design rules of a semiconductor device, thereby making it difficult to obtain desirable pitch sizes.
As a substitute, a phase shift mask has been proposed which implements precise and detailed patterns by reducing optical interference between the neighboring patterns on the semiconductor substrate with the use of chromium and molybdenum on the quartz mask board. A current trend is to use more than one phase-shift mask to obtain desired sizes as required by tighter design rules. In addition, a phase edge phase shift mask and a masking technique used in combination with a phase mask for exposing a semiconductor device has been determined to be beneficial.
For instance, a conventional phase edge phase shift mask technique is described in U.S. Pat. No. 5,807,649. With this process, two masks are used to form the same patterns (such as gate electrodes) on a semiconductor substrate. The two masks are composed of a phase shift mask and a trim mask.
Generally, a phase shift mask defines a predetermined portion of a photoresist image overlapping an active region of the semiconductor substrate by using shifters for shifting a phase of photo light.
Trim patterns on the trim mask form an entire shape of the photoresist image extended to a field region to protect the defined predetermined portion of the image from photo exposure. The photoresist image is a pattern made to form a gate pattern.
However, if an interval between the patterns is very narrow on the trim mask, the trim patterns are likely to contain defects that are detected during a checking process after the trim mask has been fabricated.
FIG. 1a is a portion of rough diagram of a phase shift mask, according to a conventional phase edge phase shift mask. Referring to FIG. 1a, the phase shift mask (10) has two shifters (20, 20-1). The two shifters (20, 20-1) are phase shift regions where light can be transmitted and separated by a predetermined interval (1S) on the phase shift mask (10).
Light passing through one of the two shifters (20, 20-1) has a 180-degree phase difference compared to light passing through the other shifter. The phase shift mask (10) is formed by the two shifters (20, 20-1) and a dark portion (15). The dark portion is formed using chromium for defining the shifters.
FIG. 1b is a rough image pattern of a phase shift mask formed on a semiconductor substrate, according to a conventional phase edge phase shift mask. Referring to FIG. 1b, the phase shift mask (10) of FIG. 1a overlaps an active region (27) on a semiconductor substrate (25), wherein the semiconductor substrate (25) is coated with a photoresist (29). And, open regions (31, 33) corresponding to the shifters (20, 20-1) of FIG. 1a are formed on the semiconductor substrate (25).
The active region (27) is depicted by dotted lines to illustrate that the region is overlapped with the shifters (20, 20-1) of FIG. 1a, and the semiconductor substrate (25) is divided into several areas (29, 31, and 33), including area (29) with the photoresist, and areas (31, 33) without the photoresist, corresponding to the shifters (20, 20-1) of FIG. 1a. 
FIG. 1c is a portion of rough diagram of a trim mask, according to a conventional phase edge phase shift mask. Referring to FIG. 1c, the trim mask (35) is overlapped by the two shifters (20, 20-1) of FIG. 1a. The two shifters (20, 20-1) formed on the trim mask (35) are depicted by dotted lines, but the two shifters (20, 20-1) are not actually formed on the trim mask (35).
The trim mask (35) is divided into trim patterns (40, 41, 37, and 37-1) where light can not be transmitted, and a transparent region (39) where light can be transmitted. Preferably, the trim patterns are subdivided into three regions: a first trim pattern (40) having a predetermined width of 4W, and formed between the two shifters (20, 20-1); a second trim pattern (41) having a predetermined dimensions of 5W and 8W in the vertical/horizontal direction, respectively, and formed outside regions composed of the shifters (20, 20-1); and third trim patterns (37, 37-1) having the same width of 3W and overlapping the shifters (20, 20-1), and the third trim patterns (37, 37-1) are in contact with the second trim pattern (41).
The second trim pattern (41) is positioned away from a right boundary of the shifter (20-1) by a predetermined distance of 6W, and the third trim pattern (37-1) is positioned inside and away from the right boundary of the shifter (20-1) by a predetermined distance of 7W.
In other words, the second trim pattern (41) and the third trim pattern (37-1) are positioned away from the right boundary of the shifter (20-1) in opposite directions of one other, thereby forming a notch structure at a check point (1P).
The notch structure is a defect that can be detected at the check point (1P) in an inspection step after the trim mask (35) is fabricated. In other words, if a width of the notch structure is out of specification as compared to the tolerances as defined by a design rule at the check point (1P), an inspection process detects the notch structure as a defect.
Further, a portion of the notch structure overlaps a portion of the photoresist (29) of FIG. 1b. And, if light is transmitted through the portion of the notch structure that overlaps the photoresist of the trim mask (35) during a photo exposure process, an unwanted field gate image (not shown) is formed by sensitizing the photoresist (29) on the semiconductor substrate (25) of FIG. 1b. 
FIG. 1d is a rough image pattern of a trim mask formed on a semiconductor substrate, according to a conventional phase edge phase shift mask. Referring to FIG. 1d, the trim mask (35) of FIG. 1c forms rough images (40-1, 41-1). The rough image (40-1) has a predetermined width of 4W-1, and overlaps the active region (27). The rough image (41-1) includes a vertical side portion having a predetermined width of 8W-1, and a horizontal portion having a predetermined height of 5W-1 on the semiconductor substrate (25).
The rough image (41-1) is formed when light passes through the notch structure on the trim mask (35) of FIG. 1c during an exposure process. Thus, the rough image (41-1) can be transferred to a gate having a very narrow width causing an increase in the resistance and drops in the current driving capability in a gate. In other words, the performance of the gate on the semiconductor device deteriorates.
Therefore, a need exists to enforce a width of a field image to improve the performance of a gate on a semiconductor device.